Pulse Triggered Flip-Flop Design with Signal Feed through Scheme using Conditional Pulse Enhancement Technique
نویسندگان
چکیده
A low power pulse triggered flip-flop with signal feed through scheme using Conditional Pulse Enhancement technique is presented in this paper. The proposed design adopts a modified True Single Phase Clock Latch structure and employs a signal feed through scheme to enhance the delay. The long discharging path problem in conventional explicit type pulse triggered flip flops are successfully solved through this method. In order to further enhance the speed and power performance, a conditional pulse enhancement technique is employed at the discharging path. Post layout simulation results based on TSMC 180 nm technology reveals that proposed flip flop features better power delay product when compared to conventional flip flops like epDCO, CDFF, SCDFF, MHLFF, SCCER and flip flop based on signal feed through scheme.
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